1. Field of the Invention
This invention relates generally to microdevice packaging and encapsulating packages and methods of fabrication and sealing of such hardware, and more particularly to a packaging device and method for simultaneous large scale packaging of plural circuit devices at one time including the step of providing a package separation technique having convenient electrodes on plural surfaces of the individual devices.
2. Description of Related Art
The following art defines the present state of this field:
Karp, U.S. Pat. No. 3,349,481 describes the process of manufacturing sealed micro-circuitry modules including networks of integrated deposited circuit elements, comprising the steps of: (a) providing circuit packaging members including an insulating glass substrate having a raised ridge surrounding a circuit-element-receiving cavity recessed below the ridge to a depth at least equaling the height of the elements to be deposited; (b) applying to the substrate spaced conductive metalized connector films, each having an external portion extending to a location outside of said packaging members for the purpose of providing external connections for the network elements when deposited within the cavity, and each extending into a location within the circuit-element-receiving cavity; (c) firing the films onto the surface to which they are applied; (d) subsequently depositing circuit-element networks in the recessed cavity including depositing portions of elements is overlapping relationship with said connector film portions located within the cavity; and (e) sealing the circuitry by applying a cover member over the recessed cavity and bonding it to the raised ridge while leaving exposed at least part of said external portion of each connector film.
Dougherty, U.S. Pat. No. 4,193,082 describes the coating of a conductor pattern on dielectric green sheets to a common edge thereof with stacking or superimpositioning together of a plurality of sheets to enclose the conductor pattern followed by sintering, with the edge side of the fired body having the exposed end terminations becoming the actual face of the body on which a semiconductor device is mounted in electrical circuit connection to respective ones of the common end terminations of the conductor runs. The opposite or distal ends of the conductor runs may be fanned out to the opposite edge of side of the fired body in increased spaced relationship to each other.
Gogal, U.S. Pat. No. 4,288,841 describes a semiconductor device including a double cavity semiconductor chip carrier 100 which comprises a multilayer ceramic sandwich structure having a pair of semiconductor chip receiving cavities in the opposite faces thereof. The package enables mounting and electrical interconnection of a pair of semiconductor integrated circuit chips in a package of the same size as that for a single chip and having somewhat greater thickness. External terminals 93 on an outside face of the carrier are connected selectively by metallization paths 44, 53, 55, 83 integral with the carrier to chip mounting pads 41, 51 and to internal terminals 28 within the carrier. The internal terminals are disposed peripherally with respect to the chip cavities and adapted for interconnection with chip contact pads 26. Thus, a pair of unlike semiconductor integrated circuits can be interconnected in accordance with different patterns within a single package.
Gilbert et al., U.S. Pat. No. 4,551,746 describes a carrier apparatus for mounting logic components on the surface of a circuit board. The carrier apparatus includes a housing structure defining top and bottom surfaces and further defining a cavity in the bottom surface for receipt of a logic component. A recessed cover portion is attached to the housing so as to enclose the cavity thereby effectively sealing the logic component in the housing. The carrier apparatus includes means for mounting the housing on a circuit board such that the cover does not make contact with the surface of the circuit board. The housing further includes means for electrically interconnecting the logic component to the circuit board. In yet another embodiment, a carrier apparatus for mounting logic components on the surface of a circuit board is disclosed which utilize ground and voltage planes together with alternating signal and AC ground traces so as to effectuate coplanar/strip-line and coplanar/microstrip transmission line environments along portions of the signal traces. Consequently, this results in signal lines having a controlled impedance environment and minimized crosstalk between neighboring signal leads lying in the same plane.
Bitaillou et al., U.S. Pat. No. 4,830,264 describes a method of forming solder terminals for a pinless module, preferably for a pinless metalized ceramic module. The method is comprised of the following steps: forming a substrate having a pattern of conductors formed onto its top surface and preformed via-holes extending from the top to bottom surface; applying a droplet of flux at least one of said preformed via-hole openings of the bottom surface of said substrate to fill said via-holes with flux by capillarity and form a glob of flux at the bottom openings; applying a solder preform, i.e. solder balls on each glob of flux to which it will adhere, the volume of the preform being substantially equal to the inner volume of the via hole plus the volume of the bump to be formed; heating to cause solder reflow of the solder preform to fill the via-hole and the inner volume of the eyelet with solder; and, cooling below the melting point of the solder so that the molten solder solidifies to form solder terminals at the via-hole locations while forming solder columns in the via-holes. The resultant pinless metalized ceramic module has connections between the I/O's of the module interfacing with the next level of packaging, (i.e., printed circuit boards), that consist of integral solder terminals. Each integral solder terminal comprises a column in the vias of the metalized ceramic substrate, a mound of solder at the top surface of the substrate and spherical solder bumps on the bottom level for making interconnections with the next level of packaging.
Ehlert et al., U.S. Pat. No. 5,168,344 describes hermetic package designs for HDMI substrates. The designs for a hermetically sealed, perimeter-leaded package may have the following features: a) a flat monolithic dielectric base, the base having a flat upper surface and a flat lower surface; b) a zone on the upper surface, in which zone the HDMI device would reside; c) a seal ring surrounding the zone; d) a cover adapted to be hermetically sealed to the seal ring, thereby protecting the HDMI device located in the zone; e) a plurality of conductive vias (inner vias) extending from the upper surface inside said zone downwardly toward the lower surface; f) a plurality of perimeter conductive lead pads located on or in the upper surface about the perimeter of the zone inside the seal ring; wherein (1) the perimeter lead pads are electrically connected to the inner vias, and (2) the inner vias are electrically connected to a surface of the base outside the zone.
Sugimura, U.S. Pat. No. 6,346,432 describes external connection terminals on side surfaces, a back surface, or both the side surfaces and the back surface of a semiconductor element, especially an optical element such as an image sensor, a solid state imaging device, etc. The external connection terminals are connected electrically to an integrated circuit of the optical element via wirings. The wirings are connected electrically to electrical measuring electrodes in the course of wafer process, but the electrical measuring electrodes are disconnected from the wirings after the electrical measurement has been completed. The electrical measuring electrodes are formed on dicing lines and then removed at the same time when dicing process is executed. The external connection terminals are connected to the wirings from which the electrical measuring electrodes are disconnected.
Pace, U.S. Pat. No. 6,388,264 describes a compact, rugged, optocoupler which is a self-contained package. The optocoupler has a photon emitter mounted on the conductive pattern of a first, inorganic substrate, and a photon detector mounted on the conductive pattern of a second, inorganic, insulating substrate. The first and second substrates are bonded to an inorganic frame to form a cell containing a photon emitter opposite a photon detector. The first and second substrates and the frame also constitute the walls of the self-contained package. The optocoupler package may be manufactured with one or multiple cells in a package.
Mayo Foundation, WO 84/01470 describes a carrier apparatus for mounting logic components on the surface of a circuit board. The carrier apparatus includes a housing structure defining top and bottom surfaces and further defining a cavity in the bottom surface for receipt of a logic component. A recessed cover portion is attached to the housing so as to enclose the cavity thereby effectively sealing the logic component in the housing. The carrier apparatus includes means for mounting the housing on a circuit board such that the cover does not make contact with the surface of the circuit board. The housing further includes means for electrically interconnecting the logic component to the circuit board. In yet another embodiment, a carrier apparatus for mounting logic components on the surface of a circuit board is disclosed which utilize ground and voltage planes together with alternating signal and AC ground traces so as to effectuate coplanar/strip-line and coplanar/microstrip transmission line environments along portions of the signal traces. Consequently, this results in signal lines having a controlled impedance environment and minimized crosstalk between neighboring signal leads lying in the same plane.
Motorola, Inc., WO 02/41397 describes a low profile integrated module that is fabricated to include sheets of material, such as ceramic or PCB, fixed together and including a via extending through at least one of the plurality of sheets from the lower module surface partially to the upper module surface and in a side module surface. The via is filled with conductive material. The module is then mounted on a supporting substrate having a solder pad on the mounting surface with an area greater than the lower surface of the via. The lower surface of the via is positioned adjacent the upper surface of the mounting pad and soldered so that solder wicks up' the via along the side module surface.
Our prior art search with abstracts described above teaches: a semiconductor element having external connection terminals and a method of manufacturing the element, a double cavity semiconductor chip carrier, a ceramic electronic package design, an integrated circuit sealing method and structure, a multi-layer dielectric structure, an hermetically sealed optocoupler package, a method of forming solder terminals on a pin-less ceramic module, a leadless chip carrier apparatus providing an improved transmission line environment with improved heat dissipation, a leadless chip carrier for logic components, and low profile integrated module interconnects. However, the prior art fails to teach a large scale integrated circuit devices package and method of making and using the package for sealing a plurality of devices at one time and a technique for dicing for obtaining the devices after encapsulation wherein the devices have external connects available to top, side and bottom surfaces. The present invention fulfills these needs and provides further related advantages as described in the following summary.